The present invention relates to the field of semiconductor technology. Specifically, embodiments of the invention are directed to transistor device structures and their manufacturing methods.
As semiconductor memory devices become increasingly integrated, the feature size including the channel length of individual devices is gradually reduced. This causes a short channel effect and also increases the junction leakage current. Leakage current was not a significant problem in the past, but it has become a more serious concern now that transistor gates and other chip components measure only a few atoms thick. In a notebook computer, leakage current means short battery life and in a server computer, it means higher power bills. Also, in a nonvolatile memory device, the leakage current leads to degradation of data retention time and other electrical characteristics as the device feature size is reduced.
Further, in small geometry devices, the threshold voltage is often difficult to control, and junction leakage current also becomes more difficult to control. Therefore, there is a need for an improved transistor device structure.
In a FinFET (Fin Field Effect Transistor), the conducting channel is built in a thin silicon “fin”, which forms the body of the device. The wrap-around gate structure provides a better electrical control over the channel and thus, helps in reducing the leakage current and overcoming other short-channel effects.
In some conventional FinFET devices, the source/drain regions are formed by first removing the portions of the Fin structure that are not covered by the gate electrode, and then using epitaxial growth to form the source/drain regions that are attached to the channel regions.